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| SSM40N03P N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low gate charge Simple drive requirement Fast switching G D S BVDSS R DS(ON) ID TO-220 30V 17m 40A Description Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220 package is widely preferred for commercial and industrial applications and suited for low voltage applications such as DC/DC converters and high efficiency switching circuits. D G S Absolute Maximum Ratings Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current 1 Rating 30 20 40 30 169 50 0.4 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 2.5 62 Unit C/W C/W Rev.2.01 7/01/2004 www.SiliconStandard.com 1 of 6 SSM40N03P Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 30 1 Typ. 0.037 Max. Units 17 23 3 1 25 100 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=10V, ID=20A VGS=4.5V, ID=16A 14 20 26 17 3 10 7.2 60 22.5 10 800 380 133 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C) o o VDS=VGS, ID=250uA VDS=10V, ID=20A VDS=30V, VGS=0V VDS=24V,VGS=0V VGS= 20V ID=20A VDS=24V VGS=5V VDS=15V ID=20A RG=3.3 ,VGS=10V RD=0.75 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol IS ISM VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=1.3V 1 Min. - Typ. - Max. Units 40 169 1.3 A A V Pulsed Source Current ( Body Diode ) Forward On Voltage 2 Tj=25C, IS=40A, VGS=0V Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. Rev.2.01 7/01/2004 www.SiliconStandard.com 2 of 6 SSM40N03P 150 T C =25 C 150 o V G =10V V G =8.0V ID , Drain Current (A) T C =150 o C V G =10V V G =8.0V ID , Drain Current (A) 100 V G =6.0V 100 V G =6.0V 50 50 V G =4.0V V G =4.0V V G =3.0V 0 V G =3.0V 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 28 1.80 I D = 2 0A 26 I D =20A 1.60 T C =25 o C 24 V G =10V 22 Normalized RDS(ON) 1.40 RDSON (m ) 20 1.20 18 1.00 16 0.80 14 12 3 4 5 6 7 8 9 10 11 0.60 -50 0 50 100 150 V GS (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature Rev.2.01 7/01/2004 www.SiliconStandard.com 3 of 6 SSM40N03P 50 60 45 50 40 35 ID , Drain Current (A) 40 25 PD (W) 30 30 20 20 15 10 10 5 0 25 50 75 100 125 150 0 0 50 100 150 T c , Case Temperature ( C) o T c ,Case Temperature ( C) o Fig 5. Maximum Drain Current vs. Fig 6. Typical Power Dissipation Case Temperature 1000 1 DUTY=0.5 Normalized Thermal Response (R thjc) 100 0.2 10us ID (A) 100us 10 0.1 0.1 0.05 0.02 0.01 PDM SINGLE PULSE t T 1ms 10ms T c =25 C Single Pulse o Duty factor = t/T Peak Tj = P DM x Rthjc + TC 100ms 10 100 1 1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance Rev.2.01 7/01/2004 www.SiliconStandard.com 4 of 6 SSM40N03P f=1.0MHz 16 10000 Id=20A 14 V D =16V VGS , Gate to Source Voltage (V) 12 V D =20V V D =24V 10 C (pF) 8 1000 Ciss 6 Coss 4 2 Crss 0 0 5 10 15 20 25 30 35 40 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 100 3 10 T j = 150 o C 2 T j = 25 o C 1 VGS(th) (V) 1 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 -50 0 50 100 150 IS (A) 0.1 0.01 V SD (V) T j , Junction Temperature ( o C ) Fig 11. Forward Characteristic of Reverse Diode Fig 12. Gate Threshold Voltage vs. Junction Temperature Rev.2.01 7/01/2004 www.SiliconStandard.com 5 of 6 SSM40N03P VDS RD 90% D VDS TO THE OSCILLOSCOPE 0.5x RATED VDS RG G 10% + 10 V S VGS VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE QG 5V D G S + 0.8 x RATED VDS QGS QGD VGS 1~ 3 mA IG ID Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.01 7/01/2004 www.SiliconStandard.com 6 of 6 |
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